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? semiconductor components industries, llc, 2001 january, 2001 rev. 9 1 publication order number: cs5111/d cs5111 1.4 a switching regulator with 5.0 v, 100 ma linear regulator with watchdog, reset and enable the cs5111 is a dual output power supply integrated circuit. it contains a 5.0 v 2%, 100 ma linear regulator, a watchdog timer, a linear output voltage monitor to provide a power on reset (por) and a 1.4 a current mode pwm switching regulator. the 5.0 v linear regulator is comprised of an error amplifier, reference, and supervisory functions. it has low internal supply current consumption and provides 1.2 v (typical) dropout voltage at maximum load current. the watchdog timer circuitry monitors an input signal (wdi) from the microprocessor. it responds to the falling edge of this watchdog signal. if a correct watchdog signal is not received within the externally programmable time, a reset signal is issued. the externally programmable active reset circuit operates correctly for an output voltage (v lin ) as low as 1.0 v. during power up, or if the output voltage shifts below the regulation limit, reset toggles low and remains low for the duration of the delay after proper output voltage regulation is restored. additionally a reset pulse is issued if the correct watchdog is not received within the programmed time. reset pulses continue until the correct watchdog signal is received. the reset pulse width and frequency, as well as the power on reset delay, are set by one external rc network. the current mode pwm switching regulator is comprised of an error amplifier with selectable feedback inputs, a current sense amplifier, an adjustable oscillator, and a 1.4 a output power switch with antisaturation control. the switching regulator can be configured in a variety of topologies. the cs5111 is load dump capable and has protection circuitry which includes overvoltage shutdown, current limit on the linear and switcher outputs, and an overtemperature limiter. features ? linear regulator 5.0 v 2% @ 100 ma ? switching regulator 1.4 a peak internal switch 120 khz maximum switching frequency 5.0 v to 26 v operating supply range ? smart functions watchdog reset enable ? protection overvoltage overtemperature current limit ? 54 v peak transient capability ? internally fused leads in so24l package http://onsemi.com so24l dwf suffix case 751e 1 24 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week marking diagram 1 cs5111 awlyyww 24 pin connections gnd gnd gnd gnd gnd gnd gnd gnd i bias v sw v lin nc v reg nc enable v in reset v fb1 c delay v fb2 124 c osc comp wdi select device package shipping ordering information cs5111ydwf24 so24l 31 units/rail cs5111ydwfr24 so24l 1000 tape & reel
cs5111 http://onsemi.com 2 figure 1. block diagram v fb1 v fb2 select comp i bias c osc v reg c delay wdi multiplexer oscillator overvoltage bandgap reference switcher error amplifier comp logic + + base drive current sense amplifier + linear error amplifier + 1.4 a v in v sw gnd enabl e v lin reset switcher shutdown current limit over temperature 1.25 v reset & watchdog timer absolute maximum ratings* rating value unit logic inputs/outputs (enable , select, wdi, reset ) 0.3 to v lin v v lin 0.3 to 10 v in , v reg: dc input voltage peak transient voltage (40 v load dump @ 14 v v in ) 0.3 to 26 0.3 to 54 v v v sw peak transient voltage 54 v c osc , c delay , comp, v fb1 , v fb2 0.3 to v lim v power dissipation internally limited v lin output current internally limited v sw output current internally limited reset output sink current 5.0 ma esd susceptibility (human body model) 2.0 kv esd susceptibility (machine model) 200 v storage temperature 65 to 150 c lead temperature soldering: reflow: (smd styles only) (note 1.) 230 peak c 1. 60 second maximum above 183 c. *the maximum package power dissipation must be observed.
cs5111 http://onsemi.com 3 electrical characteristics (5.0 v v in 26 v and 40 c t j 150 c, c out = 100 m f (esr 8.0 w ), c delay = 0.1 m f, r bias = 64.9 k w , c osc = 390 pf, c comp = 0.1 m f; unless otherwise specified.) characteristic test conditions min typ max unit general i in off current 6.6 v v in 26 v, i sw = 0 a 2.0 ma i in on current 6.6 v v in 26 v, i sw = 1.4 a 30 70 ma i reg current i lin = 100 ma, 6.6 v v in 26 v 6.0 ma thermal limit guaranteed by design 160 210 c 5.0 v regulator section v lin output voltage 6.6 v v reg 26 v, 1.0 ma i lin 100 ma 4.9 5.0 5.1 v dropout voltage (v reg v lin ) @ i lin = 100 ma 1.2 1.5 v overvoltage shutdown 30 34 38 v line regulation 6.6 v v reg 26 v, i lin = 5.0 ma 5.0 25 mv load regulation v reg = 19 v, 1.0 ma i lin 100 ma 5.0 25 mv current limit 6.6 v v reg 26 v 120 ma dc ripple rejection 14 v v reg 24 v 60 75 db reset section low threshold (v rtl ) v lin decreasing 4.05 4.25 4.45 v high threshold (v rth ) v lin increasing 4.2 4.45 4.7 v hysteresis v rth v rtl 140 190 240 mv active high v lin > v rth , i reset = 25 m a v lin 0.5 v active low v lin = 1.0 v, 10 k w pullup from reset to v lin v lin = 4.0 v, i reset = 1.0 ma 0.4 0.7 v v delay invalid wdi 6.25 8.78 11 ms power on delay v lin crossing v rth 6.25 ms watchdog input (wdi) vih peak wdi needed to activate reset 2.0 v vil 0.8 v hysteresis note 2. 25 50 mv pullup resistor wdi = 0 v 20 50 100 k w low threshold 6.25 8.78 11 ms floating input voltage 3.5 v wdi pulse width 5.0 m s switcher section minimum operating input voltage 5.0 v switching frequency refer to figure 5 80 95 110 khz switch saturation voltage i sw = 1.4 a 0.7 1.1 1.6 v output current limit 1.4 2.5 a max switching frequency v sw = 7.5 v with 50 w load, refer to figure 5 120 khz 2. guaranteed by design, not 100% tested in productions.
cs5111 http://onsemi.com 4 electrical characteristics (continued) (5.0 v v in 26 v and 40 c t j 150 c, c out = 100 m f (esr 8.0 w ), c delay = 0.1 m f, r bias = 64.9 k w , c osc = 390 pf, c comp = 0.1 m f; unless otherwise specified.) characteristic unit max typ min test conditions switcher section (continued) v fb1 regulation voltage 1.206 1.25 1.294 v v fb2 regulation voltage 1.206 1.25 1.294 v v fb1 , v fb2 input current v fb1 = v fb2 = 5.0 v 1.0 m a oscillator charge current c osc = 0 v 35 40 45 m a oscillator discharge current c osc = v40 270 320 370 m a c delay charge current c delay = 0 v 35 40 45 m a switcher max duty cycle v sw = 5.0 v with 50 w load, v fb1 = v fb2 = 1.0 v 72 85 95 % current sense amp gain i sw = 2.3 a 7.0 v/v error amp dc gain 67 db error amp transconductance 2700 m a/v enable input vil 0.8 1.24 v vih 1.3 2.0 v hysteresis 60 mv input impedance 10 20 40 k w select input vil (selects v fb1 ) 4.9 v lin 5.1 0.8 1.25 v vih (selects v fb2 ) 4.9 v lin 5.1 1.25 2.0 v select pullup select = 0 v 10 24 50 k w floating input voltage 3.5 4.5 v pin function description package pin # so24l pin symbol function 1 v in supply voltage. 2, 3 nc no connection. 4 v sw collector of npn power switch for switching regulator section. 5, 6, 7, 8, 17, 18, 19, 20 gnd connected to the heat removing leads. 9 v fb1 feedback input voltage 1 (referenced to 1.25 v). 10 v fb2 feedback input voltage 2 (referenced to 1.25 v). 11 select logic level input that selects either v fb1 or v fb2 . an open selects v fb2 . connect to gnd to select v fb1 . 12 comp output of the transconductance error amplifier. 13 c osc a capacitor connected to gnd sets the switching frequency. refer to figure 5. 14 wdi watchdog input. active on falling edge. 15 c delay a capacitor connected to gnd sets the power on reset and watchdog time. 16 reset reset output. active low if v lin is below the regulation limit. if watchdog timeout is reached, a reset pulse train is issued.
cs5111 http://onsemi.com 5 pin function description (continued) package pin # function pin symbol so24l function pin symbol 21 i bias a resistor connected to gnd sets internal bias currents as well as the c osc and c delay charge currents. 22 v lin regulated 5.0 v output from the linear regulator section. 23 v reg input voltage to the linear regulator and the internal supply circuitry. 24 enable logic level input to shut down the switching regulator. typical performance characteristics 0 20 40 100 i lin (ma) 3.5 4.5 i reg i lin (ma) 4.0 60 80 0 0.5 1.0 2.0 i sw (a) 40 0 i in (ma) 20 1.5 10 30 0 0.5 1.0 2.0 i sw (a) 0 1.4 v sw (v) 1.0 1.5 1.2 0.8 0.6 0.4 0.2 0 500 1000 3000 c osc (pf) 0 180 frequency (khz) 80 1500 160 40 140 120 100 60 20 2000 2500 figure 2. 5.0 v regulator bias current vs. load current figure 3. supply current vs. switch current figure 4. switch saturation voltage figure 5. oscillator frequency (khz) vs. c osc (pf), assuming r bias = 64.9 k
cs5111 http://onsemi.com 6 circuit description v reg overvoltage + bandgap reference 1.25 v i bias r bias 64.9 k w c delay wdi reset & watchdog timer over temperature current limit linear error amplifier r 1 q 2 q 1 q 3 r 2 r 3 r 4 r 5 v lin c out = 100 m f esr < 8.0 w reset figure 6. block diagram of 5.0 v linear regulator portion of the cs5111 5.0 v linear regulator the 5.0 v linear regulator consists of an error amplifier, bandgap voltage reference, and a composite pass transistor. the 5.0 v linear regulator circuitry is shown in figure 6. when an unregulated voltage greater than 6.6 v is applied to the v reg input, a 5.0 v regulated dc voltage will be present at v lin . for proper operation of the 5.0 v linear regulator, the i bias lead must have a 64.9 k w pull down resistor to ground. a 100 m f or larger capacitor with an esr < 8.0 w must be connected between v lin and ground. to operate the 5.0 v linear regulator as an independent regulator (i.e. separate from the switching supply), the input voltage must be tied to the v reg lead. as the voltage at the v reg input is increased, q 1 is turned on. q 1 provides base drive for q 2 which in turn provides base current for q 3 . as q 3 is turned on, the output voltage, v lin , begins to rise as q 3 's output current charges the output capacitor, c out . once v lin rises to a certain level, the error amplifier becomes biased and provides the appropriate amount of base current to q 1 . the error amplifier monitors the scaled output voltage via an internal voltage divider, r 2 through r 5 , and compares it to the bandgap voltage reference. the error amplifier output or error signal is an output current equal to the error amplifier's input differential voltage times the transconductance of the amplifier. therefore, the error amplifier varies the base current to q 1 , which provides bias to q 2 and q 3 , based on the difference between the reference voltage and the scaled v lin output voltage. control functions the watchdog timer circuitry monitors an input signal (wdi) from the microprocessor. it responds to the falling edge of this watchdog signal which it expects to see within an externally programmable time (see figure 7). the watchdog time is given by: t wdi 1.353 c delay r bias using c delay = 0.1 m f and r bias = 64.9 k w gives a time ranging from 6.25 ms to 11 ms assuming ideal components. based on this, the software must be written so that the watchdog arrives at least every 6.25 ms. in practice, the tolerance of c delay and r bias must be taken into account when calculating the minimum watchdog time (t wdi ). reset v reg wdi v lin normal operation t por figure 7. timing diagram for normal regulator operation if a correct watchdog signal is not received within the specified time a reset pulse train is issued until the correct watchdog signal is received. the nominal reset signal in this case is a 5 volt square wave with a 50% duty cycle as shown in figure 8.
cs5111 http://onsemi.com 7 figure 8. timing diagram when wdi fails to appear within the preset time interval, t wdi reset v reg wdi v lin t por ab 50% duty cycle a: watchdog waiting for lowgoing transition on wdi b: reset stays low for t wdi time the reset signal frequency is given by: f reset 1 2(t wdi ) the power on reset (por) and low voltage reset use the same circuitry and issue a reset when the linear output voltage is below the regulation limit. after v lin rises above the minimum specified value, reset remains low for a fixed period t por as shown in figures 9 and 10. figure 9. the power on reset time interval (t por ) begins when v lin rises above 4.45 v (typical) reset v lin t por 4.45 v 4.25 v v r(peak) v r(lo) figure 10. reset signal is issued whenever v lin falls below 4.25 v (typical) t por reset 5.0 v 5.0 v 4.25 v v lin the por delay (t por ) is given by: t por 1.353 c delay r bias current mode pwm switching circuitry the current mode pwm switching voltage regulator contains an error amplifier with selectable feedback inputs, a current sense amplifier, an adjustable oscillator and a 1.4 a output power switch with antisaturation control. the switching regulator and external components, connected in a boost configuration, are shown in figure 11. the switching regulator begins operation when v reg and v in are raised above 5 volts. v reg is required since the switching supply's control circuitry is powered through v lin . v in supplies the base drive to the switcher output transistor. the output transistor turns on when the oscillator starts to charge the capacitor on c osc . the output current will develop a voltage drop across the internal sense resistor (r s ). this voltage drop produces a proportional voltage at the output of the current sense amplifier, which is compared to the output of the error amplifier. the error amplifier generates an output voltage which is proportional to the difference between the scaled down output boost voltage (v fb1 or v fb2 ) and the internal bandgap voltage reference. once the current sense amplifier output exceeds the error amplifier's output voltage, the output transistor is turned off. the energy stored in the inductor during the output transistor on time is transferred to the load when the output transistor is turned off. the output transistor is turned back on at the next rising edge of the oscillator. on a cycle by cycle basis, the current mode controller in a discontinuous mode of operation charges the inductor to the appropriate amount of energy, based on the energy demand of the load. figure 12 shows the typical current and voltage waveforms for a boost supply operating in the discontinuous mode. notes: 1. refer to figure 5 to determine oscillator frequency. 2. the switching regulator can be disabled by providing a logic high at the enable input. 3. the boost output voltage can be controlled dynamically by the feedback select input. if select is open, v fb2 is selected. if select is low, then v fb1 is selected.
cs5111 http://onsemi.com 8 figure 11. block diagram of the 1.4 a current mode control switching regulator portion of the cs5111 in a boost configuration overvoltage bandgap reference i bias r bias 64.9 k w switcher error amplifier r 1 r 2 r 3 v lin enable v reg oscillator c osc comp comp logic current sense amplifier base drive + + switcher shutdown 1.25 v multiplexer v in v out c out v sw r s gnd 1.4 a v fb1 v fb2 select + figure 12. voltage and current waveforms for boost topology in cs5111 t i peak t t i peak i d i sw v sw v sat v in v out 0 0 0 protection circuitry if the input voltage at v reg is increased above the overvoltage threshold, the drive to the linear and switcher output transistors is shut off. therefore, v lin is disabled and v sw can not be pulled low. the current out of v lin is sensed in order to limit excessive power dissipation in the linear output transistor over the output range of 0 v to regulation. also, the current into v sw is sensed in order to provide the current limit function in the switcher output transistor. if the die temperature is increased above 160 c, either due to excessive ambient temperature or excessive power dissipation, the drive to the linear output transistor is reduced proportionally with increasing die temperature. therefore, v lin will decrease with increasing die temperature above 160 c. since the switcher control circuitry is powered through v lin , the switcher performance, including current limit, will be affected by the decrease in v lin .
cs5111 http://onsemi.com 9 application notes design procedure for boost topology this section outlines a procedure for designing a boost switching power supply operating in the discontinuous mode. step 1 determine the output power required by the load. p out i out v out (1) step 2 choose c osc based on the target oscillator frequency with an external resistor value, r bias = 64.9 k w . (see figure 5). step 3 next select the output voltage feedback sense resistor divider as follows (figure 13). for v fb1 active, choose a value for r 1 and then solve for r eq where: r eq r 1 v out v fb1 1 (2) for v fb2 active, find: v fb1 v out r eq r 1 r eq
(3) and then calculate r 2 where: r 2 v r2 i r2 v fb1 v fb2 v fb1 r eq (4) then find r 3 , where: r 3 r eq r 2 (5) figure 13. feedback sense resistor divider connected between v out and ground v out v fb1 v fb2 r 1 r 2 r 3 v r2 r eq step 4 determine the maximum on time at the minimum oscillator frequency and v in . for discontinuous operation, all of the stored energy in the inductor is transferred to the load prior to the next cycle. since the current through the inductor cannot change instantaneously and the inductance is constant, a voltsecond balance exists between the on time and off time. the voltage across the inductor during the on cycle is v in and the voltage across the inductor during the off cycle is v out v in . therefore: v in t on (v out v in )t off (6) where the maximum on time is: t on(max) 1 v in(min) v out(max) 1 f sw(min) (7) step 5 calculate the maximum inductance allowed for discontinuous operation: l (max) f sw(min) v in 2 (min) t on 2 (max) 2p out (8) where h = efficiency. usually h = 0.75 is a good starting point. the ic's power dissipation should be calculated after the peak current has been determined in step 6. if the efficiency is less than originally assumed, decrease the efficiency and recalculate the maximum inductance and peak current. step 6 determine the peak inductor current at the minimum inductance, minimum v in and maximum on time to make sure the inductor current doesn't exceed 1.4 a. i pk v in(min) t on(max) l (min) (9) step 7 determine the minimum output capacitance and maximum esr based on the allowable output voltage ripple. c out(min) i pk 8f v ripple (10) esr (min) v ripple i pk (11) in practice, it is normally necessary to use a larger capacitance value to obtain a low esr. by placing capacitors in parallel, the equivalent esr can be reduced. step 8 compensate the feedback loop to guarantee stability under all operating conditions. to do this, we calculate the modulator gain and the feedback resistor network attenuation and set the gain of the error amplifier so that the overall loop gain is 0 db at the crossover frequency, f co . in addition, the gain slope should be 20 db/decade at the crossover frequency. the low frequency gain of the modulator (i.e. error amplifier output to output voltage) is: v out v ea i pk(max) v ea(max) r load lf 2 (12) where: i pk(max) v ea(max) g csa r s 2.4 v 7 150 m 2.3 a (13) the v out /v ea transfer function has a pole at:
cs5111 http://onsemi.com 10 f p 1 ( r load c out ) (14) and a zero due to the output capacitor's esr at: f z 1 (2 esr(c out )) (15) since the error amplifier reference voltage is 1.25 v, the output voltage must be divided down or attenuated before being applied to the input of the error amplifier. the feedback resistor divider attenuation is: 1.25 v v out the error amplifier in the cs5111 is an operational transconductance amplifier (ota), with a gain given by: g ota gmz out (16) where: gm i out v in (17) for the cs5111, gm = 2700 m a/v typical. one possible error amplifier compensation scheme is shown in figure 14. this gives the error amplifier a gain plot as shown in figure 15. for the error amplifier gain shown in figure 15, a low frequency pole is generated by the error amplifier output impedance and c 1 . this is shown by the line ab with a 20 db/decade slope in figure 15. the slope changes to zero at point b due to the zero at: f z 1 (2 r 4 c 1 ) (18) figure 14. rc network used to compensate the error amplifier (ota) v out v fb1 v fb2 r 1 r 2 r 3 + 1.25 v m u x select error amplifier r 4 c 1 c 2 a pole at point c: f p 1 ( r 4 c 2) (19) offsets the zero set by the esr of the output capacitors. an alternative scheme uses a single capacitor as shown in figure 16, to roll the gain off at a relatively low frequency. step 9 finally the watchdog timer period and power on reset time is determined by: t delay 1.353 c delay r bias (20) figure 15. bode plot of error amplifier (ota) gain and modulator gain added to the feedback resistor divider attenuation g g gain (db) 0 a b pole due to error amplifier output impedance and c 1 f z = 1/(2 p r 4 c 1 ) f p = 1/( p r 4 c 2 ) 20 db/dec error amplifier gain +g c f co f p = 1/( p r load c out ) modulator gain + feedback resistor divider attenuation f z = 1/(2 p esr(c out ))
cs5111 http://onsemi.com 11 figure 16. a typical application diagram with external components configured in a boost topology v in l = 33 m h c out 88 m f (2) v out = 18 v, select > 2.0 v v out = 16 v, select < 0.8 v v in nc nc v sw gnd gnd gnd gnd v fb1 v fb2 select comp enable v reg v lin i bias gnd gnd gnd gnd reset c delay wdi c osc cs5111 5.0 v r bias 64.9 k w microprocessor c delay 0.1 m f c osc 390 pf c comp 0.33 m f (1) r 1 100 k w r 2 946 w r 3 7.5 k w 100 m f esr < 8.0 w
cs5111 http://onsemi.com 12 linear regulator output current vs. input voltage figure 17. the shaded area shows the safe operating area of the cs5111 as a function of i lin , v reg , and ja . refer to table 1 for typical loads and voltages. 0 5 10 30 v reg (v) 0 i lin (ma) 15 100 75 50 25 20 25 0510 30 v reg (v) 0 i lin (ma) 15 100 75 50 25 20 25 q ja = 55 c/w v in = 14 v max total power = 1.18 w q ja = 35 c/w v in = 14 v max total power = 1.86 w table 1. v reg (v) v in (v) i lin (ma) linear power dissipation (w) worst case switcher power available ( q ja = 55 c/w) (w) worst case switcher power available ( q ja = 35 c/w) (w) 20 14 25 0.44 0.74 1.42 20 14 50 0.83 0.35 1.03 20 14 75 1.22 * 0.64 20 14 100 1.60 * 0.26 25 14 25 0.60 0.58 1.26 25 14 50 1.11 0.07 0.75 25 14 75 1.62 * 0.24 25 14 100 2.14 * * *subjecting the cs5111 to these conditions will exceed the maximum total power that the part can handle, thereby forcing it int o thermal limit.
cs5111 http://onsemi.com 13 package dimensions so24l dwf suffix case 751e04 issue e notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. a b p 12x d 24x 12 13 24 1 m 0.010 (0.25) b m s a m 0.010 (0.25) b s t t g 22x seating plane k c r x 45 m f j dim min max min max inches millimeters a 15.25 15.54 0.601 0.612 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.41 0.90 0.016 0.035 g 1.27 bsc 0.050 bsc j 0.23 0.32 0.009 0.013 k 0.13 0.29 0.005 0.011 m 0 8 0 8 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 package thermal data parameter so24l unit r q jc typical 9 c/w r q ja typical 55 c/w
cs5111 http://onsemi.com 14 notes
cs5111 http://onsemi.com 15 notes
cs5111 http://onsemi.com 16 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402745 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. cs5111/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland

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